Minimizing power has become a major design objective for a lot of designers today. However, managing power effectively in a design flow has become extremely difficult since it involves making tradeoffs such as timing-versus-power and area-versus-power at different stages of the design flow. In order to achieve this efficiently, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with – and applied throughout – the entire RTL-to-GDSII flow.
This tutorial describes the most significant power dissipation and distribution considerations and highlights the requirements for a true low-power design environment. It then takes the designer through such a flow and introduces them to various techniques that can be used throughout the RTL-to-GDSII flow to manage power.
The attendees will learn how to apply various techniques at the synthesis stage such as power-aware clock gating. They will then be introduced to a methodology for doing designs with multiple voltage domains. This includes partitioning the design into different domains, placement of cells into the appropriate domains, addition of level shifters, as well as applying optimization and analysis across the different domains.
The attendees will learn how to perform power-aware cell placement based on activity to minimize dynamic power consumption. Voltage drop analysis will be performed at various stages and the results from early voltage drop analysis will be used to make adjustments to the floorplan or the power grid, if needed. Transient analysis that accounts for the capacitive and inductive effects will be demonstrated and the attendees will learn how to perform what-if analysis with on-chip decoupling capacitors to minimize these transients.
Another common problem faced by designers is the excessive margin that is built into the power grids. The attendees will be introduced to a unique approach for performing power grid synthesis. They will learn how to perform power grid synthesis and automatically come up with the optimal power grid sizes based on certain user-defined constraints.
The tutorial will also introduce the attendees to techniques for addressing leakage power by performing optimization throughout the flow that takes advantage of cells from libraries with multiple threshold voltages.
Hardware: The tools will run on SUN and Linux computers.
For more information please contact:
Sameer Patel of Magma at sameer@magma-da.com
Vassilios Gerousis at Vassilios.Gerousis@infineon.com
Minimizing power has become a major design objective for a lot of designers today. However, managing power effectively in a design flow has become extremely difficult since it involves making tradeoffs such as timing-versus-power and area-versus-power at different stages of the design flow. In order to achieve this efficiently, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with – and applied throughout – the entire RTL-to-GDSII flow.